1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to data processing systems for performing arithmetic operations suitable for performing saturated arithmetic operations.
2. Description of the Prior Art
Many DSP algorithms use what is sometimes known as Q15 arithmetic and Q31 arithmetic. A Q15 number is an ordinary 16-bit 2's complement integer, but is regarded as representing that integer divided by 2.sup.15. Since a 16-bit 2's complement integer can represent numbers from -2.sup.15 to +2.sup.15 -1, a Q15 can represent numbers from -1 to +(1-2.sup.-15).
Similarly, a Q31 number is an ordinary 32-bit 2i's complement integer, regarded as being divided by 2.sup.31, and is able to represent numbers from -1 to +(1-2.sup.-31). (N+1)-bit QN numbers can be defined analogously for any other value of N.
An important feature of Q15 and Q31 arithmetic is that they are "saturating". If the mathematical arithmetic result of an operation exceeds the maximum positive value (+1-2.sup.-N), then the saturated result is the maximum positive value; similarly, if the mathematical result is less than -1, then the saturated result is -1. For example, in Q15 arithmetic, if A=0.times.8000 (representing -1) and B=0.times.C0000 (representing -0.5), then adding A and B will produce a result of 0.times.8000 (representing -1) rather than the normal 16-bit 2's complement result of 0.times.4000.
A highly desirable and commonly occurring operation in DSP algorithms is a "multiply-accumulate", i.e. a multiplication of two operands followed by the additional of a third operand: EQU Result=(A*B)+C
Significant problems arisc when wishing to provide such multiply-accumulate instructions for saturated (sometimes known as clipped) arithmetic. This is particularly the case when performing arithmetic on QN numbers.
In order to accommodate the various different types of instruction in both saturated and non-saturated form a considerable amount of opcode bit space is required. Furthermore, when seeking to provide single cycle multiply performance, the additional burden of having to cope with the requirements for saturation and associated adjustments is such that the clock speed is undesirably limited by the worst-case saturated multiply instruction.